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Table 2-1 · CorePCIF Common Source Files
Common Files
corepcif
pci_components
fifoif
target64
burst64
add_cntr64
add_phase64
config
datapath
parity64
dma
dma_reg
26
Description
This is the top level of the core. It includes all the top-level ports. Parameters will enable and disable the Target,
Master, and backend functions as well as switching between 32- and 64-bit operation.
This is the VHDL package that contains the component declarations used within the core along with some common
type conversion functions.
This is the control logic that manages internal data storage and performs FIFO recovery cycles.
This is the top level of the main PCI Target function.
This is the main control logic used to handle the PCI protocol and manage data transfers to and from the PCI bus.
This is the main address counter that tracks both the current PCI and backend addresses.
This block compares the PCI address during an address phase to detect whether the configuration space or one of the
BARs on the Target is being addressed. It also contains the logic to detect BAR overflows so a Target disconnect can
be triggered.
This block contains the registers required to implement PCI configuration space.
This block routes the data between the backend interface or memory buffer and the PCI bus. It provides a data storage
register used to recover when transferred data are stalled.
This block creates the top-level structure for parity generation and checking. The parity generation and checking is
done using the cbe_par module.
This is the main Master control logic. It contains state machines and counters that control the DMA engine and
initiate PCI cycles.
This module contains the four DMA control registers and the main DMA transfer counters.
v4.0
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